Analog (ADC)
Every Core tile includes a general-purpose analog-to-digital converter with flexible resolution, hardware oversampling, and built-in sensors for temperature and supply voltage. The ADC is fully supported by both the core_ API and the Hardware Abstraction Layer (HAL).
6, 8, 10, or 12-bit on all cores.
2–9 external channels per core, depending on tile pad count.
2× to 256× hardware averaging (1024× on Core.H). Extends effective resolution up to 16-bit on all cores.
Up to ~1 Msps at 12-bit (varies by core and clock). Peak ~2.86 Msps at 8-bit on Core.H (theoretical, minimum sampling time).
Continuous background conversion with DMA and per-sample callbacks — no CPU polling needed.
On-die temperature sensor (factory-calibrated) and VDDA supply measurement via VREFINT.
core_adc for pad-level reads with automatic channel mapping, or hal_adc when you need direct control over channels, oversampling, or DMA buffers.The ADC instance and channel numbering vary by core — Core.W uses ADC4 on AHB4, while all others use ADC1. See for the full mapping.