SPI

Overview

You pick an SPI instance (SPI1, …), a clock prescaler, and the clock polarity/phase (CPOL / CPHA — the four standard SPI modes). Chip-select is a regular GPIO you drive around each transaction, so one bus can address many devices.

Transfers

Init, point chip-select at a tile pad, then transact. transfer is one full-duplex byte (send and receive at once); xfer wraps a multi-byte transfer in select/deselect for you:

#include "core.h"

  hal_spi_t spi;
  hal_spi_config_t cfg = { .prescaler = LL_SPI_PRESCALER_8, .cpol = 0, .cpha = 0 };
  core_spi_init(&spi, SPI1, &cfg);
  core_spi_set_cs(&spi, 8);            // chip-select on tile pad 8

  core_spi_select(&spi);
  uint8_t id = core_spi_transfer(&spi, 0x9F);   // e.g. flash JEDEC ID
  core_spi_deselect(&spi);

  uint8_t tx[4] = { 0x03, 0, 0, 0 }, rx[4];
  core_spi_xfer(&spi, tx, rx, sizeof(tx));      // select + xfer + deselect

DMA transfers

For large transfers, hand the buffers to DMA and get a callback on completion — the CPU is free in the meantime. Both buffers must stay valid until the callback fires:

static void on_done(void *ctx) { /* transfer complete */ }

  if (core_spi_xfer_dma(&spi, tx, rx, len, on_done, NULL) != HAL_OK) {
      // busy, or a bad length
  }
  while (core_spi_busy(&spi)) { /* or go do other work */ }

Cross-architecture support

Polled master transfers and DMA are verified on every Core that has SPI; interrupt and target (slave) modes are still ahead. The same core_spi contract holds where the peripheral exists:

See the implementation status for the full matrix.

Known gaps

What the SDK itself lists as missing here, straight from the header:

API reference

int core_spi_xfer_byte_bus(uint8_t bus, uint8_t cs_pad, uint8_t tx);

hal_status_t core_spi_init(hal_spi_t * h, SPI_TypeDef * instance, const hal_spi_config_t * cfg);

hal_status_t core_spi_configure(hal_spi_t * h, const hal_spi_config_t * cfg);

uint32_t core_spi_sck_hz(const hal_spi_t * h);

void core_spi_set_cs(hal_spi_t * h, uint8_t pad);

void core_spi_select(hal_spi_t * h);

void core_spi_deselect(hal_spi_t * h);

uint8_t core_spi_transfer(hal_spi_t * h, uint8_t tx);

hal_status_t core_spi_exchange(hal_spi_t * h, const uint8_t * tx, uint8_t * rx, uint32_t len);

hal_status_t core_spi_write(hal_spi_t * h, const uint8_t * data, uint32_t len);

hal_status_t core_spi_read(hal_spi_t * h, uint8_t * buf, uint32_t len);

hal_status_t core_spi_xfer(hal_spi_t * h, const uint8_t * tx, uint8_t * rx, uint32_t len);

hal_status_t core_spi_write_read(hal_spi_t * h, const uint8_t * tx, uint32_t tx_len, uint8_t * rx, uint32_t rx_len);

hal_status_t core_spi_exchange_dma(hal_spi_t * h, const uint8_t * tx, uint8_t * rx, uint32_t len);

hal_status_t core_spi_xfer_dma(hal_spi_t * h, const uint8_t * tx, uint8_t * rx, uint32_t len, hal_callback_t cb, void * ctx);

hal_status_t core_spi_dma_wait(hal_spi_t * h);

int core_spi_busy(hal_spi_t * h);

hal_spi_t * core_spi_handle_for_bus(uint8_t bus);