UART

Overview

A UART is identified by its USART instance (USART1, USART2, …). You give it a baud rate; everything is 8 data bits, no parity, 1 stop bit (8N1). The peripheral clock is resolved for you, so init is just the instance and a baud rate.

core_serial is handle-based (Tier 1): you hold a hal_uart_t and pass it to each call. There’s also a small Tier 2 *_bus surface (print / putc by config-declared bus id) for Studio.

Transmit

The usual path needs no init code. Assign the pads in config.json and coregen emits a ready handle, core_usart<n>, set up inside core_init() at the baud you give (115200 by default). Then write strings, bytes, or formatted output. TX is blocking: the call returns once the bytes are on the wire:

// config.json (Core.ST.L0 pads; each Core's definition lists its own):
  //   "pads": { "7": "USART2.TX", "2": "USART2.RX" },
  //   "interfaces": { "USART2": { "baud": 115200, "rx_interrupt": true } }

  #include "core.h"
  #include "core_serial.h"

  core_init();                                   // brings up core_usart2
  core_serial_print(&core_usart2, "boot\r\n");
  core_serial_printf(&core_usart2, "adc=%u mv=%lu\r\n", raw, mv);

rx_interrupt turns on interrupt-driven receive into a ring buffer (see below). To bring up a USART by hand instead, fill a config and call core_serial_init():

hal_uart_t uart;
  hal_uart_config_t cfg = { .baud = 115200, .rx_interrupt = 0 };
  core_serial_init(&uart, USART2, &cfg);

Receive

RX has two modes, chosen at init. With rx_interrupt = 0 you poll; with rx_interrupt = 1 the driver fills a background ring buffer you drain at your own pace:

hal_uart_config_t cfg = { .baud = 115200, .rx_interrupt = 1 };
  core_serial_init(&uart, USART2, &cfg);

  // later, in your loop:
  while (core_serial_available(&uart)) {
      uint8_t b = core_serial_getc(&uart);   // blocking; pair with available()
      handle(b);
  }

DMA transmit

Cross-architecture support

Polling TX/RX is the verified baseline; interrupt-driven RX and LPUART are further along on some Cores than others. The same core_serial contract holds across the family:

See the implementation status for the full matrix.

Known gaps

What the SDK itself lists as missing from serial, straight from the header:

API reference

int core_serial_print_bus(uint8_t bus, const char * str);

int core_serial_putc_bus(uint8_t bus, uint8_t byte);

hal_status_t core_serial_init(hal_uart_t * h, USART_TypeDef * instance, const hal_uart_config_t * cfg);

hal_status_t core_serial_init_clk(hal_uart_t * h, USART_TypeDef * instance, uint32_t pclk_hz, const hal_uart_config_t * cfg);

void core_serial_write(hal_uart_t * h, const uint8_t * data, uint32_t len);

void core_serial_print(hal_uart_t * h, const char * str);

void core_serial_putc(hal_uart_t * h, uint8_t byte);

uint16_t core_serial_available(hal_uart_t * h);

uint8_t core_serial_getc(hal_uart_t * h);

uint16_t core_serial_read(hal_uart_t * h, uint8_t * buf, uint16_t max_len);

hal_uart_t * core_serial_handle_for_bus(uint8_t bus);